Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

As CMOS scaling options are exhausted by fundamental limitations, device and circuit integration in the third-dimension could provide a possible pathway without extensively relying on ultra-scaled transistors. So far, however, the migration of CMOS to 3-D has been unattainable. The CMOS fabric architecture uses complementary MOSFETs in an inverted logic, where both pull-up and pull-down transistors share the same input. The C-MOSFETs have opposite doping profiles and each MOSFET contains multiple doping regions. In order to achieve correct circuit operation, these MOSFETs have to be carefully sized and doped precisely in a 3-D stack. In terms of connectivity, a 3-D implementation of CMOS circuits would imply that each input signal has to be vertically routed twice for C-MOSFETs. Mapping such connectivity in 3-D even for a 4 fan-in logic gate, where pull-down transistors are stacked and pull-up transistors are isolated, or vice versa, would result in connectivity bottlenecks; for a large circuit these issues would become unmanageable. In terms of manufacturing, CMOS in 3-D would imply extreme lithography to create various vertical shapes for 3-D C-MOSFETs with each MOSFET doped precisely in isolated 3-D regions, which is impractical. In addition to these, there is no heat extraction capability inherent to CMOS to prevent thermal hotspot development. Admittedly, since the inception of vertical devices in 2000 6 there has been no success in the realization of 3-D CMOS despite a significant industrial push. In contrast to CMOS, that has evolved focusing on the device especially and requires a largely component-centric assembly, the Skybridge fabric shifts to a fabric-centric mindset and provides an integrated solution for all technology aspects. First, it starts with a regular array of uniform vertical nanowires that forms the Skybridge template (Fig. 1A). Second, its doping requirement is uniform, without regions, and done once at the wafer level. Finally, the various features of the fabric are realized through functionalizing this template with material deposition techniques. All inserted material structure features, regarding device, circuit style, connectivity, thermal management, are co-architected for 3-D requirements, compatibility, manufacturability, and overall efficiency, even if tradeoffs needed to be made on individual aspects. Vertical Junctionless transistors that do not require doping variations are implemented on these nanowires, and are accommodated in new Skybridge circuit styles supporting both logic and volatile memory in 3-D and using only single-type and uniformly sized transistors. Further, nanowires are linked with structures referred to as Skybridge Bridges for connectivity. …